Cross Talk
Crosstalk is the one which pinches over at the end faces of
the design cycle.
Topics on which the crosstalk will hamper through a chip
design cycle.
When we go through a design there are three things we need
to take care while designing.
1.
Power:
We look for a lowest consumption on the chip. For eg. Mobile phones need to be
operated for more hours (more than a day).
2. Performance: Again with the same eg of mobile
phones, there are over 10 applications it has to work with same speed, how many
may be the applications the working speed should be the same for each and every
application.
3. Area: Always the smaller handsets are preferred
compared to the bigger ones. In the smaller area they need same number of
multiple applications to run with max performance
Crosstalk is the one which hampers all of the above
mentioned three. So the emphasis on crosstalk has been increased in the recent
trends where we go for sub 100nm node (nanometer technology), for eg 90nm 65
nm, 45 nm, 28nm, 20nm. Crosstalk is the one which is hampering the achieved
power, performance, and area. Where the crosstalk comes from.
Considering industrial standards some of topics are taken
under crosstalk
1.
Reasons for crosstalk: Reasons behind the
inception of crosstalk, where does the crosstalk starts coming from, one of the
eg we can discuss right away is, if 100s of application runs in a chip, there
are millions of transistors switching over each over all over the chip, which is
turn result in crosstalk. Late the other reasons will be discussed.
2.
Introduction to Noise margin: Crosstalks have to
be quantified based on certain thresholds. This threshold is modelled in terms
of noise margin. Voltage across various existing levels are taken and try to
define certain threshold that identify the crosstalk. Some signal crosses
certain voltage levels that will suffer to noise, other hand if the certain
signal at some other voltage level are safe. Those things are discussed in this
topic which deals with DC noise margin.
3.
Crosstalk Glitch example: Considering real time
eg how the crosstalk got evolved. On the nearby circuit path we can identify
that the near-by nets that is actually impacting the victim. Those real time eg
are cover under this topic.
4.
Factors affecting the glitch height: WE try to
reduce the glitch height as far as possible by tuning the factors affecting the
glitch height.
5.
AC Noise margin: Modelling the noise margin only
based on DC noise margin will become very pessimistic so we need to come up
with accurate approach for determining noise that is the AC noise margin. It accurately determines which are accurately safe
and unsafe noises and fix only those, instead of fixing all of them.
6.
Timing window concepts: If multiple aggressors
coming together and affecting common victim which is very unlikely. Those
multiple aggressors affecting for certain period of time, that timing window
will be looking into this particular concept.
7.
Impact of crosstalk on Setup and Hold timing
analysis: Crosstalk creates the two major types of problems. One is the noise
and other is the delta delay, it basically deals with the delay of the cell.
Here we see how it impacts the delay of the cell and also how it affects the
setup and hold timing.
8.
Techniques to reduce the Crosstalk: By finding
the techniques to reduce crosstalk and bring within the noise margin rage
either AC or DC noise margin range.
9.
Power Supply noise: We are having pin encountering
into power mesh structure when we enter into chip power design cycle and there
are reason why we went into power mesh cycle.
Crosstalk Noise Reasons and Definition
High routing density
and large number of standard cells
Increase in number of metal layers resulting in increase in lateral capacitance
Lower supply voltage
leading to lesser noise margin
Noise Margin
Let us consider an
example of an inverter
When we plot the I/O characteristics graph for the given
inverter,
When the input is 0 the output is high and vice-versa. For
the above graph when we move from 0 to Vdd in the Vin scale, the output
switches from high (Vdd) to low (0) at the Vdd/2 point of the Vin axis in the case of a CMOS inverter.
